| Breaking the simulation barrier: SRAM evaluation through norm minimization L Dolecek, M Qazi, D Shah, A Chandrakasan 2008 IEEE/ACM International Conference on Computer-Aided Design, 322-329, 2008 | 156 | 2008 |
| Challenges and directions for low-voltage SRAM M Qazi, M Sinangil, A Chandrakasan IEEE design & test of computers 28 (1), 32-43, 2010 | 111 | 2010 |
| Loop flattening & spherical sampling: Highly efficient model reduction techniques for SRAM yield analysis M Qazi, M Tikekar, L Dolecek, D Shah, A Chandrakasan 2010 Design, automation & test in Europe conference & exhibition (DATE 2010 …, 2010 | 103 | 2010 |
| A 512kb 8T SRAM macro operating down to 0.57 V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45 nm SOI CMOS M Qazi, K Stawiasz, L Chang, AP Chandrakasan IEEE Journal of Solid-State Circuits 46 (1), 85-96, 2010 | 98 | 2010 |
| A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13- CMOS for Nonvolatile Processing in Digital Systems M Qazi, A Amerasekera, AP Chandrakasan IEEE Journal of Solid-State Circuits 49 (1), 202-211, 2013 | 75 | 2013 |
| A statistical study of magnetic tunnel junctions for high-density spin torque transfer-MRAM (STT-MRAM) R Beach, T Min, C Horng, Q Chen, P Sherman, S Le, S Young, K Yang, ... 2008 IEEE International Electron Devices Meeting, 1-4, 2008 | 66 | 2008 |
| A Low-Voltage 1 Mb FRAM in 0.13m CMOS Featuring Time-to-Digital Sensing for Expanded Operating Margin M Qazi, M Clinton, S Bartling, AP Chandrakasan IEEE Journal of Solid-State Circuits 47 (1), 141-150, 2011 | 62 | 2011 |
| Low-swing signaling on monolithically integrated global graphene interconnects KJ Lee, M Qazi, J Kong, AP Chandrakasan IEEE transactions on electron devices 57 (12), 3418-3425, 2010 | 32 | 2010 |
| 40.4 fJ/bit/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45nm SOI CMOS S Park, M Qazi, LS Peh, AP Chandrakasan 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013 | 24 | 2013 |
| A low-voltage 1Mb FeRAM in 0.13 μm CMOS featuring time-to-digital sensing for expanded operating margin in scaled CMOS M Qazi, M Clinton, S Bartling, AP Chandrakasan 2011 IEEE International Solid-State Circuits Conference, 208-210, 2011 | 18 | 2011 |
| Design of low-voltage digital building blocks and ADCs for energy-efficient systems ME Sinangil, M Yip, M Qazi, R Rithe, J Kwong, AP Chandrakasan IEEE Transactions on Circuits and Systems II: Express Briefs 59 (9), 533-537, 2012 | 16 | 2012 |
| Technique for efficient evaluation of SRAM timing failure M Qazi, M Tikekar, L Dolecek, D Shah, AP Chandrakasan IEEE transactions on very large scale integration (VLSI) systems 21 (8 …, 2012 | 3 | 2012 |
| Circuit design for embedded memory in low-power integrated circuits M Qazi Massachusetts Institute of Technology, 2012 | 2 | 2012 |
| A 4kb memory array for MRAM development M Qazi Massachusetts Institute of Technology, 2007 | 1 | 2007 |
| Voice Training Karaoke Machine M Qazi, Z Zhou | | 2006 |
| Next generation MRAM development: a 4kb MRAM array for spin torque transfer switching measurement M Qazi (No Title), 0 | | |
Anantha ChandrakasanDean of Engineering, Massachusetts Institute of TechnologyVerified email at mit.edu
